As the demand for improved semiconductor device performance continues to increase, so too does the need for improved semiconductor device characterization techniques. Semiconductor wafers, such as silicon wafers, play an important role in the fabrication of device structures. Improved monitoring of device characteristics is critical in the development of advanced semiconductor device fabrication techniques. Monitoring of characteristics includes monitoring of implant and anneal processes, monitoring of emitter sheet resistance, monitoring of shunt resistance or leakage current in Si solar cell, CCD/CMOS imagers, epitaxial layers for LED applications and implant monitoring. Of particular importance in the monitoring of device structures is the monitoring of sheet resistance and shunt resistance, conductance or leakage current in p-n junctions layers. Prior art approaches to p-n junction monitoring suffers from a number of drawbacks. Prior approaches utilized overly simplified models and often require additional measurement information (e.g., capacitance) to arrive at sheet resistance values. A primary disadvantage in previous approaches is that many prior techniques are based on the assumption that a top p-n junction layer sheet resistance is significantly higher than the sheet resistance of the corresponding substrate. In many settings, this assumption is not valid, leading to significant measurement error. An additional drawback of the prior art is that surface photovoltage (SPV) at the back side of a given wafer typically contributes to the measured JPV signal from the front side of the wafer, thereby resulting in systematic error. It is evident that the prior art includes a number of deficiencies. Therefore, it would be desirable to provide a method and system that cure these deficiencies of the prior art identified above.